1. Field of the Invention
The present invention relates to memory devices that can store more than one bit per memory cell.
2. Description of the Related Art
In conventional single-bit per cell memory devices, the memory cell assumes one of two information storage states, either an “on” state or an “off” state. This combination of either “on” or “off” defines one bit of information. A memory device using such single-bit cells to store n bits of data (n being an integer greater than 0) thus requires n separate memory cells.
Increasing the number of bits which can be stored in a single-bit per cell memory device involves increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored. Methods for increasing the number of memory cells in a single memory device have relied upon advanced manufacturing techniques that produce larger chips containing more memory cells or that produce smaller memory cells (e.g., by high resolution lithography) to allow more memory cells to be placed in a given area on a single chip.
An alternative to the single-bit per cell approach involves storing multiple bits of data in a single memory cell. Previous approaches to implementing multiple-bit per cell non-volatile memory devices have typically involved mask-programmable read only memories (ROMs). In one of these approaches, the channel width and/or length of the memory cell is varied such that 2n different conductivity values are obtained which correspond to 2n different states, whereby n bits of data can be stored by a single memory cell. In another approach, the ion implant for the threshold voltage is varied such that the memory cell will have 2n different voltage thresholds (Vt) corresponding to 2n different conductivity levels corresponding to 2n different states, whereby n bits of data can be stored by a single memory cell.
Electrically alterable non-volatile memory (EANVM) devices capable of storing multiple bits of data per cell are also known. In these devices, the multiple memory states of the cell are demarcated by predetermined reference signal levels that define boundaries between adjacent memory states. The memory cell is read out by comparing a signal from the cell with the reference signals to determine the relative levels of the cell signal and the reference signals. The comparison results indicate whether the cell signal level is above or below the respective memory state boundaries, and thus collectively indicate the programmed state of the cell corresponding to the stored data. The comparison results are encoded to reproduce the stored data and complete the cell readout operation. Generally speaking, the number of reference levels required to demarcate n memory states for storing n bits of data is 2n−1. The number may be greater if, for example, the uppermost or lowermost memory state is to be bounded on both sides.
Conventional nonvolatile multilevel memories have many disadvantages, particularly at the circuit and architectural levels. Conventional multi-level memories require a large amount of wiring for reading and sensing the n number of bit per cell. The conventional multilevel approaches also have penalties on sensing speed, control complexity, and reliability. This is because the multilevel memories require very tightly programmed cell threshold voltage control. Furthermore, a high program voltage is needed to cover the wide threshold voltage range. Thus, some of the cells have to endure the high program voltages while maintaining their threshold voltages.
A need exists for a multi-bit memory cell that is simpler and that can be programmed with higher reliability compared to the conventional multi-bit memory cells.